Hi, my name is
Abdullah Hendy.
I am a computer engineer, probably because I could never pick between hardware and software — I love both. My work has always lived at the bottom of the stack: the low-level stuff. Whether it's designing and laying out PCBs, writing RTL on FPGAs, or writing bare-metal C. And even when I move up the stack and touch high-level software, I stick to system languages — shout out to Golang — building software that directly interacts with hardware. Go microservices talking to FPGAs? Yes, please.
I recently finished my Master's at UMich. During my last semester, I started working with Dr. Reetu Das on building a cycle-accurate hardware emulation for their recent PIM-based GPU-less LLM accelerator paper. I didn't realize how much LLM decoding was bottlenecked by memory bandwidth and it sparked my interest in LLM acceleration and AI infra research. Now, I'm looking for PhD opportunities to contribute to solving LLM acceleration bottlenecks so that, one day, we can run large LLMs without needing a cluster of a million GPUs.
$ cd ~/University-of-Michigan/
$ cat "Research-Assistant"
[2026 - Now]Under the guidance of Dr. Reetu Das, I work on developing a cycle-accurate hardware emulation of a CENT device
leveraging CMU's Ramulator2 DRAM simulator and other vendor-specific DDR models.
I also work on extending the open-source LiteDRAM project to support CENT-specific DRAM commands for LPDDRx models.
This work targets the Amazon F2 Cloud FPGA (XCVU47P HBM2) to validate the emulation across different GPT and LLaMA inference workloads.
$ cd ~/Keysight-Technologies/
$ cat "R&D-Engineer"
[2024 - 2025]During my time there, I worked on diverse projects. In the beginning, I developed a P4-based packet capture module inside a programmable switch pipeline to enable low-level network traffic debugging.
After that, I worked on modernizing test equipment synchronization infrastructure by implementing custom RTL logic on timing FPGAs and its supporting gRPC microservices to allow for nanosecond-level precision.
Later, I moved to AI/HPC infrastructure and worked on optimizing DMA-based data movement using PCIe Gen5 on Xilinx Versal SoC.
$ cd ~/Cirrus-Logic/
$ cat "Applications-Engineer-Intern"
[2023 - 2023]At this internship, I mainly worked on developing a unified Python API wrapping drivers of silicon emulation platforms with multiple FPGAs for internal and external customer workflows.
This helped standarize and simplify verification workflows by abstracting away underlying hardware variations across different emulation platforms.
